`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/03/31 11:40:31
// Design Name: 
// Module Name: timer
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module timer(
    input   clk,
    input   rst,
    output  [7:0]seg_data,
    output  [7:0]seg_data2,
    output  [7:0]seg_cs
    );

    integer timer_cnt;
    reg [6:0]seconds;
    reg [6:0]minutes;
    reg [5:0]hours;

    always @(posedge clk or negedge rst) begin
        if(!rst)
            begin
            timer_cnt <= 0;
            seconds <= 0;
            minutes <= 0;
            hours <= 0;
            end
        else if(timer_cnt>=100_000_000)
            begin
            timer_cnt<=0;
            if(seconds>=59)     
                begin
                seconds<=0;
                if(minutes>=59)     
                    begin
                    minutes<=0;
                    if(hours>=23)     
                        begin
                        hours<=0;
                        end
                    else    hours<=hours+1;
                    end
                else    minutes<=minutes+1;
                end
            else    seconds<=seconds+1;
            end
        else    timer_cnt <= timer_cnt+1;
    end

    reg [31:0] data;
    always @(seconds) begin
        data[31:28] = hours/10;
        data[27:24] = hours%10;
        data[23:20] = 04'hf;
        data[19:16] = minutes/10;
        data[15:12] = minutes%10;
        data[11:8]  = 04'hf;
        data[7:4]   = seconds/10;
        data[3:0]   = seconds%10;
    end
    

    number u1(  .clk(clk),
                .rst(rst),
                .data(data),
                .seg_data(seg_data),
                .seg_data2(seg_data2),
                .seg_cs(seg_cs)
            );

endmodule
